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Home / Librarys / Digital Circuit Theory & Computer Arch / Start with verilator / Example / ex-10-fifo

File   EditTime Size
f_txuart.v 2022-09-18 16:31:38 9.28 KB
job.txt 2022-09-18 16:31:38 2.48 KB
linetest.v 2022-09-18 16:31:38 3.19 KB
linetest_tb.cpp 2022-09-18 16:31:38 8.89 KB
Makefile 2022-09-18 16:31:38 2.7 KB
rxuart.v 2022-09-18 16:31:38 7.11 KB
sfifo.gtkw 2022-09-18 16:31:38 891 B
sfifo.sby 2022-09-18 16:31:38 168 B
sfifo.v 2022-09-18 16:31:38 6.03 KB
testb.h 2022-09-18 16:31:38 2.32 KB
txuart.v 2022-09-18 16:31:38 8.43 KB
uartsim.cpp 2022-09-18 16:31:38 3.27 KB
uartsim.h 2022-09-18 16:31:38 1.76 KB
2025-04-27 12:05:37 Sunday 18.116.51.45 Runningtime:0.005s Mem:456.23 KB