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Home / Librarys / Digital Circuit Theory & Computer Arch / Start with verilator / Example / ex-10-fifo

File   EditTime Size
f_txuart.v 2023-11-28 09:27:36 9.28 KB
job.txt 2023-11-28 09:27:36 2.48 KB
linetest.v 2023-11-28 09:27:36 3.19 KB
linetest_tb.cpp 2023-11-28 09:27:36 8.89 KB
Makefile 2023-11-28 09:27:36 2.7 KB
rxuart.v 2023-11-28 09:27:36 7.11 KB
sfifo.gtkw 2023-11-28 09:27:36 891 B
sfifo.sby 2023-11-28 09:27:36 168 B
sfifo.v 2023-11-28 09:27:36 6.03 KB
testb.h 2023-11-28 09:27:36 2.32 KB
txuart.v 2023-11-28 09:27:36 8.43 KB
uartsim.cpp 2023-11-28 09:27:36 3.27 KB
uartsim.h 2023-11-28 09:27:36 1.76 KB
2024-12-22 20:26:33 Sunday 18.224.60.132 Runningtime:0.005s Mem:443.75 KB